1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of controlling such semiconductor device.
2. Description of the Related Art
A NAND flash memory collectively performs write and read by “pages” (by two kilbyte (Kbyte) pages, for example). When writing, the data of one page is input from an I/O terminal (sixteen bits wide) to a page buffer in a serial fashion. In the page buffer, the latch circuits for one page are prepared for latching program data. When the data latch into the page buffer transfer is completed, programming is performed simultaneously on the subject memory cells. When reading, data is read in from the memory cells of one page, and the read data is collectively latched into the latch circuits in the page buffer. The read data is then output from the I/O terminal in a serial fashion under the control of an external device (a toggle operation of a terminal/RE pin, for example).
For high-speed writing operations, a cache programming mode has recently been suggested. In this mode, while memory cells are being programmed with write data latched in a page buffer, new write data is loaded from outside into the cache latch circuits for one page. As soon as the previous programming is completed, programming is performed with the new write data. Accordingly, the required data loading time can be shortened. Also, a copy-back mode has been suggested. In this mode, the data of one page stored in memory cells is read into a page buffer, and is written into another page with a different address. As the data read into the page buffer is not output to the outside and the copying operation is automatically performed inside, the operation time can be shortened.
Further, in this mode, new write data from outside is input into the page buffer when the cell data is read into the page buffer. Another page is then programmed with the overwritten new data (see U.S. Pat. No. 6,671,204 (Patent Document 1)).
In a conventional NAND flash memory, information is recorded by injecting charges into a floating gate made of polycrystalline silicon. Since a control gate is made of polycrystalline silicon, this flash memory is manufactured by a polysilicon double-layer process. Such memory cells are connected in series to form an array structure. In this structure, writing is performed through FN tunneling caused by generating a high potential between the control gates of each cell and the substrate.
In recent years, there have been flash memories with SONOS (semiconductor-oxide-nitride-oxide-semiconductor) cells that record information by trapping charges in a nitride film instead of a floating gate. Since each of the flash memories with this structure can be manufactured by a polysilicon one-layer process, the production costs are lower. Also, as the flash memories of this type can form a virtually grounded array structure, a higher degree of cell integration can be achieved. The interface (I/F) with the outside is the same as that of a NOR flash memory, and writing is performed through hot electron injection caused by applying a high voltage to the drain and the control gate of each subject cell (see U.S. Pat. No. 6,011,725 (Patent Document 2)).
Japanese Unexamined Patent Publication Nos. 5-298894 and 62-162299 (Patent Document 3 and Patent Document 4, respectively) also disclose techniques for faster writing operations. By either of the techniques, if the number of “0” bits (in a written state) among input data is larger than a predetermined number, the input data is inverted and then written in memory cells and flag data indicating that the input data is inverted is also written in the memory cells.
Non-Patent Document 1 (“A 512 Mb NROM flash data storage memory with 8 MB/s data rate”, E. Maayan, et al., Digest of Technical Papers, pp. 100-101, February 2002) has disclosed a flash memory having SONOS cells and a NAND I/F. In this document, a Static Random Access Memory (SRAM) that latches the data of one page (528 bytes in this disclosure) is disclosed. However, specific structures and operations are not disclosed in the document. Also, there is not a description of a cache program or a copy-back operation.
A flash memory having SONOS cells and a conventional NOR flash memory additionally has the following drawbacks. Since writing is performed through hot electron injection, the current consumption is greater than that of a NAND flash memory. Also, since the number of bits that can be programmed at one time is as small as several tens, the programming speed is low.
In a conventional NAND flash memory, on the other hand, two Kbyte cells can be programmed at once because the writing is performed through FN tunneling. However, a page buffer circuit that can cope with such high-speed programming is required, resulting in a large circuit size.